The present invention relates to a system for driving a flat type display device, and more particularly to a drive system available for various video signals which are different in the number of the scanning lines per picture, namely for multiple scanning.
Conventionally, in order to drive a flat-type display device of a matrix for displaying an image on a flat display panel, thereby providing a line-at-a-time scanning system.
FIG. 6 shows a conventional drive system for driving a liquid crystal display panel 10 of an active matrix. In the drive system, a control circuit 30, a column electrode drive circuit 20, and a row electrode drive circuit 40 are provided for line sequential scanning of the liquid crystal display panel 10.
The liquid crystal display panel 10 includes a plurality of pixels disposed in matrix of m rows x n columns. Corresponding to the pixels, gate lines Sl to Sm on m rows and data lines Dl to Dn on n columns are provided. Between the gate line and the data line, a MOS transistor 10a is connected as a switching element in each pixel.
The control circuit 30 includes a synchronous separation circuit 31 to which a video signal C is applied for separating a horizontal synchronizing signal H and a vertical synchronizing signal V of the video signal C.
The horizontal and vertical synchronizing signals H and V are applied to a vertical address generator 32. The vertical address generator 32 is initialized by the vertical synchronizing signal V and operated to count the horizontal synchronizing signal H for generating a vertical address A.
The horizontal synchronizing signal H is further applied to a dot clock generator 33 for generating a dot clock DCLK in synchronism with the horizontal synchronizing signal H in phase.
The dot clock DCLK is inputted into a horizontal address generator 34 which also receives the horizontal synchronizing signal H. The horizontal address generator 34 is initialized by the horizontal synchronizing signal H and operated to count the dot clock DCLK for generating a horizontal address A.
The horizontal address A is applied to a gate pulse generator 35 in which a gate pulse G is generated based on the horizontal address A.
The vertical address A and the gate pulse G are applied to the row electrode drive circuit 40 for producing scanning pulses. The dot clock DCLK is further applied to the column electrode drive circuit 20 for standardizing shift timing.
The column electrode drive circuit 20 comprises shifters of n-stage for converting display data in a series into parallelly arranged display data and has a holding circuit 21 for holding the video data so as to apply display data of one scanning line to the display panel 10 in parallel.
Although it is not shown, the column electrode drive circuit 20 also includes a holding circuit other than the holding circuit 21 to alternately or sequentially input and output the display data with the holding circuit 21. A data driver provides for amplifying the data held in the holding circuit 1 for applying the data to the data lines Dl to Dn.
The row electrode drive circuit 40 is provided for applying the scanning pulses to the gate lines Sl to Sm by the line sequential scanning based on the video signal. The row electrode drive circuit 40 includes a decoder 41 having a plurality of decode lines Bl to Bm, and a gate circuit 42 comprising a plurality of gates 42a provided corresponding to the decode lines Bl to Bm. Each of the decode lines Bl to Bm is connected to one of the input terminals of the corresponding gates 42a of the gate circuit 42. The other input terminal of each gate 42a is applied with the gate pulse G from the gate pulse generator 35 of the control circuit 30. An output terminal of the gate 42a is connected to each of the respective gate lines Sl to Sm.
The decoder 41 is supplied with the vertical address A from the vertical address generator 32 of the control circuit 30 for activating the decode lines Bl to Bm in order in accordance with the value of the vertical address A. A decoded signal is applied to the corresponding gate 42a in which a logical product is obtained in accordance with the gate pulse G. The gate 42a produces a scanning pulse which is applied to the display panel 10 through the corresponding gate line of Sl to Sm.
Although it is not shown, level shifters and gate drivers for amplifying the power are disposed between the gate circuit 42 and the gate lines Sl to Sm
The operation of the system now will now be described. FIG. 7 shows waveforms of the respective signals. The digital signals are unified by positive logic.
When the video signal C shown in FIG. 7a, is applied to the drive system, the control circuit 30 operates to separate the vertical synchronizing signal V and the horizontal synchronizing signal H, as shown in FIG. 7b, from the video signal C. Based on the vertical and horizontal synchronizing signals V and H, the vertical address A, gate pulse G and dot clock DCLK are generated.
The vertical address A is initialized to "0" by the vertical synchronizing signal V, and proceeds sequentially "1", "2", . . . "m " as shown in FIG. 7c, in synchronism with the horizontal synchronizing signal H.
The gate pulse G produced, based on the horizontal address A', has a pulse width corresponding to a predetermined range of the horizontal address A'. The predetermined range is a period in which data held in the holding circuit 21 is stable and determined in accordance with a period in which the scanning pulse is ready to feed. As shown in FIG. 7d, the gate pulse G represents a first interval wherein the sending of the scanning pulse is suppressed from being applied for line sequential scanning between the pulses, and a second interval where the sending of the scanning pulse is allowed to be applied by the pulse. Generally, the first interval coincides with the retrace line interval, and the second interval coincides with the horizontal scanning period. Thus, the gate pulse G is produced corresponding to the horizontal scanning period.
In the column electrode drive circuit 20, the video signal C is applied in series in synchronism with the dot clock DCLK and the display data for one horizontal scanning period is held in the holding circuit 21. The held display data is applied to the data lines Dl to Dn, which are in parallel, at a new period delayed one horizontal scanning period. At the time, a display data of a next one scanning is applied to the net holding circuit in series and held therein. At a period after the next period, the display data held in the other holding circuit is applied to the data lines Dl to Dn in parallel. Thus, the display data of the video signal C is applied to the data lines Dl to Dn by a delay of one horizontal scanning period.
In the row electrode drive circuit 40, the vertical address A is decoded by the decoder 41 to activate the decode lines B1, B2, B3, . . . in order in synchronism with the horizontal synchronizing signal H as shown in FIGS. 7e, 7f and 7g. The decoded signals of the decode lines pass the gate 42a in sequential order in accordance with the gate pulse G. Thus, the vertical scanning pulse having a pulse width corresponding to the pulse width of the gate pulse G is applied to the gate lines S1, S2, S3, . . . in sequential order, as shown in FIGS. 7h, 7i and 7j.
In the liquid crystal display panel 10, the MOS transistor 10a is connected to the gate line of Sl to Sm is turned on. Signal voltage of data lines of Dl to Dn is applied to the corresponding n electrodes. Thus, a content for displaying the picture for one field corresponding to the gate line is changed.
As the gate line applied with the scanning pulse is transferred in order, the content for displaying the picture is changed in order per unit of the row.
Recently, a high definition display having a high definition driving system has been developed. It is requested that the high definition driving system for the high definition display can be used for the standard definition display. Therefore, a driving system is developed so that the vertical scanning frequency of the video signal can be selectively changed by a computer system. In such a system, the number of vertical scanning lines in a field dependent on the video signal is changeable any time.
If a video signal for the high definition display is applied to the drive system for the high definition display device, the number of vertical scanning lines in one field of the video signal coincides with the number of entire rows of the display device (number of row electrodes). Thus, the image can be normally displayed on the display. However, if the number of vertical scanning in the field is smaller than the number of entire rows of the display device, the image is displayed on a part of the display in the vertical direction. For example, if the video signal having 480 scanning lines in the field is applied to the display device having 1000 rows and driven by the conventional drive system, the image is displayed on an upper half of the display.
Consequently, it is desirable to develop the drive system for realizing a multiple scanning which is available for video signals having a different number of scanning lines per frame. However, in view of common use of parts of circuits and miniaturization of circuits, the conventional system can be changed without largely changing the structure.